Reduction of the surface roughness of Ge-on-insulator layers up to sub-nanometer range by chemical mechanical polishing
DOI:
https://doi.org/10.24297/jap.v11i8.6821Keywords:
Ge on insulator, direct wafer bonding, chemical mechanical polishing, wet chemical etchingAbstract
We are investigating the thermoelectric characteristics of Ge and SiGe nanostructures for realizing high power generator efficiency. In this paper, we investigated the influence of the thinning process on the surface roughness of a direct wafer-bonded p-type Ge-on-insulator (GOI) layer in order to realize an ultra-thin GOI substrate with extremely low surface roughness for the fabrication of Ge and SiGe nanostructures. The wafer thinning process was performed by chemical mechanical polishing (CMP) and wet chemical etching (WCE). A very smooth GOI layer with sub-nanometer (0.3 nm) surface roughness, suitable for nanostructure fabrication, was achieved using CMP compared to WCE process.
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References
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II. Z. Chen, G. Han, L. Yang, L. Cheng and J. Zou, Nanostructured thermoelectric materials: Current research and future challenge. Progress in Natural Science: Materials International. 22, (Dec. 2012), 535-549.
III. H. Alam, and S. Ramakrishna, A review on the enhancement of figure of merit from bulk to nano-thermoelectric materials. Nano Energy. 2, (Mar. 2013), 190-212.
IV. Z. Wang, and N. Mingo, Diameter dependence of SiGe nanowire thermal conductivity. Appl. Phys. Lett. 97, (Sep. 2010), 101903.
V. Y. Moriyama, N. Hiroshita, E. Toyoda, K. Usuda, S. Nakaharai, N. Sujiyama and S. Takagi, Study of the surface cleaning of GOI and SGOI substrates for Ge epitaxial growth. ECS Transactions. 3, (Jul. 2006), 1183-1190.
VI. J. Kang, X. Yu, M. Takenaka, and S. Takagi, Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding. Materials Science in Semiconductor processing. 42, (Jul. 2015), 259-263.
VII. W. S. Jung, J. H. Nam, A. Pal, J. H. Lee, Y. Na, Y. Kim, J. H. Lee and K. C. Sarawat, Reduction of Surface Roughness in Epitaxially Grown Germanium by Controlled Thermal Oxidation. IEEE Electron Device Letters. 36, (Mar. 2015), 297-299.
VIII. T. Ohmi, K. Katoni, A. Teramoto, and M. Miyashita, Dependence of electron channel mobility on Si-SiO/sub 2/ interface microroughness. IEEE Electron Device Letters. 12, (Dec. 1991), 652-654.
IX. R. I. Hegde, M. A. Chonko and P. J. Tobin, Effect of silicon substrate microroughness on gate oxide quality. J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct. 14, (Sep. 1996) 3299-3304.
X. Z. Shi, S. Shao, and Y. Wang, Improved the surface roughness of silicon nanophotonic devices by thermal oxidation method. J. Phys., Conf. Ser. 276, (Mar. 2011), 012087.
XI. Y. Ruan, Y. Liu, W. Lin, S. Chen, C. Li, H. Lai, W. Huang and X. Zhang, Impacts of thermal annealing on hydrogen-implanted germanium and germanium-on-insulator substrates. J. Electrochem. Soc. 158, (Oct. 2011), 1125-1128.
XII. L. Wang, R. Yujiao, C. Songyan, L. Cheng, L. Hongkai and H. Wei, The impact of polishing on germanium-on-insulator substrates, Journal of Semiconductors. 34, (Aug 2013), 083005.
XIII. http://www.musashino-denshi.co.jp/
XIV. S. Kagawa, T. Mikawa and T. Kaneda, Chemical etching of germanium with H3PO4-H2O2-H2O solution. Jpn. J. Appl. Phys. 21, (Nov.1982), 1616-1618.
XV. J. Maehliss, A. Abbadie, F. Brunier and B.O. Kolbesen, Chromium(VI)-free defect etching solutions for application on engineered silicon substrates. ECS Transactions. 16, (Oct. 2008), 309-320.
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Published
2016-06-16
How to Cite
Manimuthu, V., Arivanandhan, M., Hayakawa, Y., & Ikeda, H. (2016). Reduction of the surface roughness of Ge-on-insulator layers up to sub-nanometer range by chemical mechanical polishing. JOURNAL OF ADVANCES IN PHYSICS, 11(10), 4088–4092. https://doi.org/10.24297/jap.v11i8.6821
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