Nand gate architectures for memory decoder

Authors

  • Shivkaran Jain Thapar university, Patiala
  • Arun Kr. Chatterjee Thapar University, Patiala

DOI:

https://doi.org/10.24297/ijct.v7i2.3464

Keywords:

Memory decoder, nor based nand, source coupled nand, high speed, low power

Abstract

This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed. The three designs conventional, nor style nand, source coupled nand, ranges in area, speed and power. In nor style nand transistors are added in parallel so high fan-in is obtained and logical effort is reduced. In source coupled nand number of transistors are reduced it give speed of operation compared to an inverter. When simulated and compared it is found that nor style nand is 35% faster and 67 % more power efficient than conventional. Source coupled nand is found to be 36% faster and 82% more power efficient than conventional nand gate.

Downloads

Download data is not yet available.

Author Biographies

Shivkaran Jain, Thapar university, Patiala

M.TECH. student

Arun Kr. Chatterjee, Thapar University, Patiala

Assistant Professor

Downloads

Published

2013-06-05

How to Cite

Jain, S., & Chatterjee, A. K. (2013). Nand gate architectures for memory decoder. INTERNATIONAL JOURNAL OF COMPUTERS &Amp; TECHNOLOGY, 7(2), 610–614. https://doi.org/10.24297/ijct.v7i2.3464

Issue

Section

Research Articles