Power Efficient MAC Unit Based Digital PID Controllers

Authors

  • V. Kavitha Professor, M.Kumarasamy College of Engineering, Karur, Tamilnadu, India
  • S. Mohanraj Assistant Professor,M.Kumarasamy College of Engineering, Karur,Tamilnadu, India

DOI:

https://doi.org/10.24297/jac.v12i9.4090

Keywords:

Multiply-Accumulate (MAC), Array Multiplier, Booth Multiplier, Wallace Tree Multiplier, Proportional-Integral-Derivative controllers (PID).

Abstract

Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product.

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Author Biographies

V. Kavitha, Professor, M.Kumarasamy College of Engineering, Karur, Tamilnadu, India

Department of Electronics and Communciation Engineering,

S. Mohanraj, Assistant Professor,M.Kumarasamy College of Engineering, Karur,Tamilnadu, India

Department of Electronics and Communciation Engineering,

References

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Published

2016-11-03

How to Cite

Kavitha, V., & Mohanraj, S. (2016). Power Efficient MAC Unit Based Digital PID Controllers. JOURNAL OF ADVANCES IN CHEMISTRY, 12(9), 4324–4329. https://doi.org/10.24297/jac.v12i9.4090

Issue

Vol. 12 No. 9 (2016)

Section

Articles

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Creative Commons License All articles published in Journal of Advances in Linguistics are licensed under a Creative Commons Attribution 4.0 International License.