HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS
DOI:
https://doi.org/10.24297/ijct.v10i6.7025Keywords:
Self-Checking adders, fast adders, Hybrid-CMOS Logic Style, differential XOR, carry look-ahead, Carry skip, Carry-select, Conditional-Sum adderAbstract
In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes.
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References
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[2]. Belgcem Hamdi , Chiraz Khedhiri , Aymen Fradi and Tourki Rached, "Four Transistors Self-checking Differential XOR". In Proceedings of the 10th Edition IEEE International Symposium on Signals, Circuits & Systems, Romania, June, 2011.
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[10]. Padma Devi, Ashima Girdher and Balwinder Singh, “Improved Carry Select Adder with Reduced Area and Low Power Consumption, “International Journal of Computer Applications (0975 – 8887), Volume 3 – No.4, June 2010.
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[12]. B. Hamdi, H. Bederr, M. Nicolaidis, A tool for automatic generation of self-checking data paths, in: Proceeding of 13th IEEE VLSI Test Symposium, Proceedings (VTS’95), 30 Apr-3 May 1995, pp 460 – 466.
[13]. A.Naini et al., “A 4.5 ns 96 b adder design,†in CICC Proc. pp. 25.5.1–25.5.4, 1992.
[14]. Y. Tsujihashi et al., “A high density data path generator with stretchable cells,†in CICC Proc. pp. 11.3.1–11.3.4, 1992.
[15]. B. K. Kumar and P. K. Lala, On-Line Detection of Faults in Carry-Select Adders, in Proc. Int. Test Conf., vol. 1, Charlotte, NC, Sep. 30-Oct. 2, 2003, pp. 912–918
[2]. Belgcem Hamdi , Chiraz Khedhiri , Aymen Fradi and Tourki Rached, "Four Transistors Self-checking Differential XOR". In Proceedings of the 10th Edition IEEE International Symposium on Signals, Circuits & Systems, Romania, June, 2011.
[3]. Michael Nicolaidis, On-line testing for VLSI: state of the art and trends, Integration, the VLSI Journal, Volume 26, Issues 1-2, 1 December 1998, pp. 197-209.
[4]. D. K. Pradhan, J. J. Stiffler, Error correcting codes and self-checking circuits in fault-tolerant computers. IEEE Computer Mag. Vol. 13, March 1980, pp. 27-37.
[5]. A.P. Chandrakasan, S. Sheng and R. W. Brodersen, Low-Power CMOS Digital Design. IEEE Journal of Solid State Circuits, Vol. 27, No. 4, April 1992, pp. 473–484.
[6]. D. A. Anderson and G. Metze, Design of totally self-checking check circuits for m-out-of-n codes. IEEE Trans. on Computers, vol. 22, No. 3, March 1973, pp. 263-269.
[7]. P. Oikonomakos, M. Zwolinski, On the Design of Self-Checking Controllers with Datapath Interactions. IEEE Transactions on Computers, Volume 55, No 11, Nov 2006, pp. 1423 – 1434.
[8]. M. Nicolaidis, L. Anghel, Concurrent Checking in VLSI. Microelectronic Engineering, Vol. 49, Nov 1999, pp 139- 156.
[9]. A.Tyagi, “A reduced area scheme for carry-select addersâ€, IEEE Trans. on Computer, vol. 42, pp. 1163- 1170, 1993
[10]. Padma Devi, Ashima Girdher and Balwinder Singh, “Improved Carry Select Adder with Reduced Area and Low Power Consumption, “International Journal of Computer Applications (0975 – 8887), Volume 3 – No.4, June 2010.
[11]. M. Nicolaidis, Efficient implementations of self-checking adders and ALUs, in: Proceeding of 23rd International Symposium on Fault-Tolerant Computing, June 1993, pp. 586-595.
[12]. B. Hamdi, H. Bederr, M. Nicolaidis, A tool for automatic generation of self-checking data paths, in: Proceeding of 13th IEEE VLSI Test Symposium, Proceedings (VTS’95), 30 Apr-3 May 1995, pp 460 – 466.
[13]. A.Naini et al., “A 4.5 ns 96 b adder design,†in CICC Proc. pp. 25.5.1–25.5.4, 1992.
[14]. Y. Tsujihashi et al., “A high density data path generator with stretchable cells,†in CICC Proc. pp. 11.3.1–11.3.4, 1992.
[15]. B. K. Kumar and P. K. Lala, On-Line Detection of Faults in Carry-Select Adders, in Proc. Int. Test Conf., vol. 1, Charlotte, NC, Sep. 30-Oct. 2, 2003, pp. 912–918
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Published
2013-10-23
How to Cite
HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS. (2013). INTERNATIONAL JOURNAL OF COMPUTERS &Amp; TECHNOLOGY, 10(6), 1771–1778. https://doi.org/10.24297/ijct.v10i6.7025
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