HIGH SPEED CARRY SAVE MULTIPLIER BASED LINEAR CONVOLUTION USING VEDIC MATHAMATICS
Keywords:Linear convolution, Urdhva - Tiryagbhyam, carry save multiplier, Verilog HDL.
AbstractVLSI applications include Digital Signal Processing, Digital control systems, Telecommunications, Speech and Audio processing for audiology and speech language pathology. The latest research in VLSI is the design and implementation of DSP systems which are essential for above applications. The fundamental computation in DSP Systems is convolution. Convolution and LTI systems are the heart and soul of DSP. The behavior of LTI systems in continuous time is described by Convolution integral whereas the behavior in discrete-time is described by Linear convolution. In this paper, Linear convolution is performed using carry save multiplier architecture based on vertical and cross wise algorithm of Urdhva â€“ Tiryagbhyam in Vedic mathematics. Coding is done using Verilog HDL(verilog Hardware Description Language). Simulation and Synthesis are performed using Xilinx FPGA
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How to Cite
Reddy, B., Rani, D. L., & Varadarajan, P. S. (2013). HIGH SPEED CARRY SAVE MULTIPLIER BASED LINEAR CONVOLUTION USING VEDIC MATHAMATICS. INTERNATIONAL JOURNAL OF COMPUTERS &Amp; TECHNOLOGY, 4(2), 284–287. https://doi.org/10.24297/ijct.v4i2a2.3173