HIGH SPEED CARRY SAVE MULTIPLIER BASED LINEAR CONVOLUTION USING  VEDIC MATHAMATICS

Bharathi Reddy; D. Leela Rani; Prof. S. Varadarajan

doi:10.24297/ijct.v4i2a2.3173

Authors

Bharathi Reddy Assistant Professor, Department of ECE, Sree Vidyanikethan Engineering College, Tirupati, India
D. Leela Rani 2Associate Professor, Department of ECE, Sree Vidyanikethan Engineering College, Tirupati,
Prof. S. Varadarajan 3Professor, Department of ECE, SVU College of Engineering, Tirupati.

DOI:

https://doi.org/10.24297/ijct.v4i2a2.3173

Keywords:

Linear convolution, Urdhva - Tiryagbhyam, carry save multiplier, Verilog HDL.

Abstract

VLSI applications include Digital Signal Processing, Digital control systems, Telecommunications, Speech and Audio processing for audiology and speech language pathology. The latest research in VLSI is the design and implementation of DSP systems which are essential for above applications. The fundamental computation in DSP Systems is convolution. Convolution and LTI systems are the heart and soul of DSP. The behavior of LTI systems in continuous time is described by Convolution integral whereas the behavior in discrete-time is described by Linear convolution. In this paper, Linear convolution is performed using carry save multiplier architecture based on vertical and cross wise algorithm of Urdhva â€“ Tiryagbhyam in Vedic mathematics. Coding is done using Verilog HDL(verilog Hardware Description Language). Simulation and Synthesis are performed using Xilinx FPGA