Circuit Optimization For Transmission Gate Master Slave Flip-Flops

Abstract

In this work, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay, power, and area minimization is worthwhile to improve the performance in high-speed designs[1]. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path[1]. Simulations have been performed at transistor level on several well-known TGMS FFs, designed in 65-nm and 90nm technologies using Microwind3.1 CAD tool, and the results have been compared to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements have been found on delay, power and on area occupation, thus showing that this approach allows correctly dealing with the actual path in such circuits and hence to more properly steering the design towards the achievement of efficiency in the high-speed region[1]. epaE� n � �� RGMCET, Nandyal,maheswari.mmr@gmail.com