A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX
Keywords:Power Delay Product, High and Low threshold voltages, parasitic capacitances, Area
This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.
How to Cite
All articles published in Journal of Advances in Linguistics are licensed under a Creative Commons Attribution 4.0 International License.