EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER

DOI:

https://doi.org/10.24297/ijct.v12i5.2915

Keywords:

VLSI, FPGA

Abstract

Most of the algorithms which are used in DSP, image and video processing, computer graphics, vision and high performance supercomputing applications require multiplication and matrix operation as the kernel operation.In this paper, we propose Efficient FPGA based matrix multiplication using MUX and Vedic multiplier. The 2x2, 3x2 and 3x3 MUX based multipliers are designed. The basic lower order MUX based multipliers are used to design higher order MxN multipliers with a concept of UrdhvaTiryakbyham Vedic approach. The proposed multiplier is used for image processing applications. It is observed that the device utilization and combinational delay are less in the proposed architecture compared to existing architectures.

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Published

2014-01-30

How to Cite

EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER. (2014). INTERNATIONAL JOURNAL OF COMPUTERS &Amp; TECHNOLOGY, 12(5), 3452–3463. https://doi.org/10.24297/ijct.v12i5.2915

Issue

Section

Research Articles