A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL
Keywords:Pixefeeder, DVI, pixelcounter, SDR2DDR, I2CDRAM master, FIFO initial, PLL.
There is a definite need for video and image processing technologies in today's world. However the computer vision technologies need to be tested and optimized. There is need for testing these interfaces for the platform which we work on. This modeling is a cost effective architecture for interfacing Digital Visual Interface(DVI) on Virtex5 FPGA's. The architecture is modeled in such a way that it does not use XPS micro blaze or Power PCÂ processor but simple pixel feeder design, configuration of the Chrontel 7301C chip design and the interface between them.