A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL

Authors

  • Asif Ahmad A S BMS COLLEGE OF ENGINEERING,ACCREDITED BY NBA BANGALORE

DOI:

https://doi.org/10.24297/ijct.v13i2.2905

Keywords:

Pixefeeder, DVI, pixelcounter, SDR2DDR, I2CDRAM master, FIFO initial, PLL.

Abstract

There is a definite need for video and image processing technologies in today's world. However the computer vision technologies need to be tested and optimized. There is need for testing these interfaces for the platform which we work on. This modeling is a cost effective architecture for interfacing Digital Visual Interface(DVI) on Virtex5 FPGA's. The architecture is modeled in such a way that it does not use XPS micro blaze or Power PC  processor but simple pixel feeder design, configuration of the Chrontel 7301C chip design and the interface between them.


Downloads

Download data is not yet available.

Author Biography

Asif Ahmad A S, BMS COLLEGE OF ENGINEERING,ACCREDITED BY NBA BANGALORE

ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENTUSN:1BM12EC022

Downloads

Published

2014-04-12

How to Cite

A S, A. A. (2014). A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL. INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY, 13(2), 4230-4236. https://doi.org/10.24297/ijct.v13i2.2905

Issue

Section

Research Articles