Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing

Authors

  • Shilpa Sathish VISVESVARAYA TECHNOLOGICAL UNIVERSITY
  • C. Lakshminarayana B.M.S.C.E, Bangalore, India,

DOI:

https://doi.org/10.24297/ijct.v2i3b.2699

Keywords:

VLSI, power consumption, critical path, DFG, Unfolding

Abstract

The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts

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Author Biography

Shilpa Sathish, VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Dr A.I.TELECTRONICS AND COMMUNICATION

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Published

2012-06-30

How to Cite

Sathish, S., & Lakshminarayana, C. (2012). Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing. INTERNATIONAL JOURNAL OF COMPUTERS &Amp; TECHNOLOGY, 2(3), 96–101. https://doi.org/10.24297/ijct.v2i3b.2699

Issue

Section

Research Articles