JAIN, S.; CHATTERJEE, A. K. Nand gate architectures for memory decoder. INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY, [S. l.], v. 7, n. 2, p. 610–614, 2013. DOI: 10.24297/ijct.v7i2.3464. Disponível em: https://rajpub.com/index.php/ijct/article/view/3464. Acesso em: 19 may. 2024.