EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER. INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY, [S. l.], v. 12, n. 5, p. 3452–3463, 2014. DOI: 10.24297/ijct.v12i5.2915. Disponível em: https://rajpub.com/index.php/ijct/article/view/2915. Acesso em: 25 dec. 2024.