SATHISH, S.; LAKSHMINARAYANA, C. Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing. INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY, [S. l.], v. 2, n. 3, p. 96–101, 2012. DOI: 10.24297/ijct.v2i3b.2699. Disponível em: https://rajpub.com/index.php/ijct/article/view/2699. Acesso em: 21 dec. 2024.