DESIGN OF CMOS LOW DROP-OUT REGULATORS: A COMPARATIVE STUDY

The advancement in battery operated portable devices, noise sensitive devices and other devices, which need high precision supply voltages has fuelled the growth of Low Drop-Out Regulators. Low Drop-Out Regulators showed advantage over its counterpart. The design of Low Drop-Out Regulators with high performance and less Die area is challenging problem now-a-days. This paper is a study of various techniques that are used to achieve better performance of low drop-out regulators.


INTRODUCTION
Supplying and conditioning power are the most elementary functions of an electrical system. Any loading application, such as a pager, cellular phone and bio-medical devices can not sustain itself without energy, and can not fully perform its functions without a stable supply. The fact is transformers, generators, batteries, and other off-line supplies get substantial voltage and current variations across time and over a wide range of operating conditions. They are normally jittery and noisy not only because of their inherent nature but also because high-power switching circuits like digital signal-processing circuits (DSP) and central-processing units (CPUs) usually load these devices. The rapidly changing loads cause transient excursions in the supposedly noise-free supply, the end results of which are undesired voltage drops and frequency boosts where only a dc component should exist [1]. Use of switching power supply or DC to DC converter, provides portable applications to operate in noisy environments. Mostly electronic systems are very sensitive to noise present on power supplies. Consequently, they require large battery filters to reduce the ripple on battery voltage [2]. The explosive proliferation of battery-powered equipment in the past decade has accelerated the development and use of Low Drop-out voltage regulators for noise sensitive circuits [2,3]. Low drop-out regulators is driven by the growing demand for higher performance power supply circuits [4]. The low drop-out nature of the regulator makes it suitable for use in many applications, namely, automotive, portable and biomedical applications. The automotive industry requires low drop-out regulators to power up digital circuits, especially during cold-crank conditions where the battery voltage can be below 6 V. The increasing demand, however, is especially appear in mobile battery operated products, such as cellular phones, pagers, camera recorders, and laptops. In a cellular phone, for instance, switching regulators are used to boost up the voltage but LDO's are cascaded in series to suppress the inherent noise associated with switching regulators. LDO's benefit from working with low input voltages because power consumption is minimized accordingly, P . Low voltage and low quiescent current are intrinsic circuit characteristics for increased battery efficiency and longevity. Low voltage operation is also a consequence of process technology. This is because isolation barriers reduce as the component densities per unit area increase, thereby exhibiting lower breakdown voltages. Therefore, low power and finer lithography require regulators to operate at low voltages, produce precise output voltages, and have characteristically lower quiescent current flow [5]. The thrust is towards reducing the number of battery cells, required to decrease cost and size, while minimizing quiescent current flow to increase battery life. Current efficiency is particularly important because at low load-current conditions the life of battery is adversely affected by low current efficiency in other words, high quiescent current flow [6]. In this paper, different techniques to improve the performance parameters of low drop-out regulators will be covered. The organization of this paper is as follows: Section 2 will introduce the LDO block description and specifications. Section 3 will cover the structures of LDO with capacitors and discussion of special topology used in designing the LDO. Section 4 will discuss the LDO topologies with external capacitor free architecture. Experimental results will be included in Section 5. Finally in section 6 conclusion of this paper will be discussed. The Voltage Reference provides a precise output voltage for the operation of the regulator. Voltage references, unlike regulators, have a poor load driving capability.
The Error Amplifier produces an error signal whenever the sensed feedback output differs from the reference voltage. The error output is used to control the amount of current the pass element allows into the load. The resulting control seeks to set the value of output voltage ( ) to a level where the error signal is as close as possible to zero.
The Pass Element provides the output current needed to drive the load, under the control of the error amplifier. Several configurations of the pass element have been proposed, depending on the system specification. The most widely used configurations include NMOS transistor and common source PMOS transistor. PMOS transistors are typically the best overall choice yielding a good compromise of dropout voltage, quiescent current flow, output current, and speed. The circuit design of an LDO is thoroughly affected by the physical requirements of the pass element. The pass element must be physically large to yield high output currents and low dropout voltage characteristics.
The Feedback Network produces the output voltage to be compared with the voltage reference. This voltage is produced by a voltage divider described by the equation 1. (1) Feedback network can be designed using passive elements (resistors) or active elements (transistors) [7].

LOW DROP-OUT REGULATORS
Low drop-out regulators provide constant supply rail suitable for power management. On the basis of stability and chip area, LDO are of two types namely Low Drop-Out Regulators with Capacitor and Low Drop-out Regulators without capacitor. Capacitor free LDO utilises external capacitor for stability on the cost of chip area. Chip area problem can be solved by using on-chip LDO, which utilises the different compensation techniques for stability without using external capacitor. Detail discussion on LDOs with capacitor and capacitor free LDOs are discussed in sections 3.1 and 3.2 respectively.

Low drop-out regulators with capacitor
The several authors have been reported low drop-out regulators with capacitor [9][10][11][12][13][14]. Leung et al. [9] proposed a low drop-out structure to reduce board space. The structure utilises damping-factor control frequency compensation scheme along with first-order high-pass feedback network. Due to virtue of this scheme, this structure provides high stability, load transient and fast line load transient responses. Adaptive miller compensation (AMC) technique based LDO structure in [10] provides high stability, as well as fast line and load transient responses. This structure also provides good performance on PSRR at high frequency. However, there are some disadvantages with this structure. The gain-band width (GBW) of this LDO is directly proportional to trans-conductance of pass device, which depends on output current, so it is not suitable for large current design. Oh et al. [11] presented an LDO with current feedback amplifiers (CFAs) as shown in Fig. 2. The suggested LDO provides fast response and high slew rate with class-AB operation. CMOS LDO has measure problem of high impedance feedback path which has been solved in the suggested structure. This structure utilizes a low ac impedance feedback path to achieve fast response while maintaining low quiescent power consumption. The low ac impedance feedback path is constructed using a CFA based second-stage buffer. CFAs are popular to provide fast response with minimum slew-rate limiting. It uses global voltage mode feedback for steady state accuracy. The LDO structure with an impedance attenuated buffer for driving the pass device has been suggested in [12].
In the structure error amplifier has been realised by single-stage folded-cascode structure. This LDO structure is stabilized by using current-buffer (or cascode-Miller) frequency compensation, which is a pole-splitting compensation designed for splitting of two poles. The use of the current-buffer compensation scheme allows the amplifier to achieve wider unity-gain frequency, improved stability and enhance PSRR. Man et al. [13] presented a LDO structure using flipped voltage follower (FVF) cell. By using FVF in the structure, the output impedance is reduced which provides better stability than conventional LDO. The loop bandwidth at low load current is independent of the load current. It has wider bandwidth than the conventional LDO. The LDO structure based on CFA with inverting output buffer suggested in [14] is shown in Fig. 3. Very low impedance at the inverting input of the CFA is the reason to achieve high regulation and fast transient response of this structure. The use of CFA in the circuit gives excellent performance in terms of bandwidth and slew rate.

Capacitor free low drop-out regulators
Capacitor free low drop-out regulators have several advantages over the low drop-out regulators with capacitance discussed in section 3.1 on the basis of small size and portability. Hazucha et al. [15] proposed a LDO structure, which uses replica-biased source follower for multi-supply voltage. This topology achieves very fast response time and good figure of merit which accounts for the decoupling capacitance, output drop, current efficiency and current rating. The LDO structure with a capacitor-multiplier frequency compensation technique suggested in [16] is shown in Fig. 4. This technique eliminates the cascode structure or buffer stage, due to which suggested LDO facilitates low voltage operation. Shiyang et al. [17] has been presented a LDO using Damping-factor-control (DFC) block along with miller compensation shown in Fig. 5.

Fig. 5 Structure of LDO with DFC Block [17]
By using Miller compensation, a low frequency dominant pole is internally generated, and two other non-dominant poles, which frequency are higher than unity gain frequency (UGF), which is configured by DFC block. DFC block is placed in between first and second stage. Stability has been achieved by Miller and DFC compensation, through the opposed zero cancellation. A capacitor less LDO structure with an input current differencing technique to achieve sleep-mode efficiency and area saving is proposed in [18]. Instead of using an operational amplifier as the error amplification block, it consists of a current differencing (CD) stage. There were two main advantages when the techniques were implemented in an LDO. Firstly, it allows low voltage operation. Secondly, this configuration renders a smaller feedback factor that helps reducing the excessive loop gain that threatens stability in zero loads. Kamal et al. [19] proposed a topology which does not require an external capacitor for their stability. They use PMOS as pass device and implement a compensation circuitry in between output of error amplifier and drain of pass devices for improving its performance over uncompensated system. A LDO with NMOS as a pass device proposed in [20] consists of an error amplifier, a floating voltage source, the pass element, and the feedback network. This architecture uses switched floating capacitors to take advantage of using NMOS transistor as a pass device. Wang et al. [21] have suggested high precision low dropout regulator with nested feedback loops. A zero-tracking compensation loop is nested inside of the negative feedback loop comprising an error amplifier. It utilises PMOS transistor as pass device. This structure is independent of off-chip capacitor and effective series resistance (ESR).

COMPARISON
Low drop-out regulators with capacitor and without capacitor low drop-out regulator are discussed in sections 3.1 & 3.2 and their simulated results are tabulated in Tables 1 & 2, respectively. From Table 1, it can be seen that the LDO suggested in [14] has higher regulation, current efficiency and PSRR than the existing LDOs. It can also be observed that low drop-out regulators with capacitor occupy large area due to the use of load capacitor for stability.    [21] has higher PSRR and regulation than the existing LDOs. Due to the use of special compensation schemes and topologies high regulation, current efficiency and PSRR is achieved without using external capacitor. Also these structures occupy less chip area with desired performance specifications such as current efficiency, regulation and PSRR.

CONCLUSION
A Low Drop-Out Regulator is capable of keeping its specified output voltage over a wide range of load current and input voltage. LDO provide constant supply rail for integrated circuits. Many of the LDOs in today's portable devices are integrated into multifunction Power-management integrated circuits. Stability is major concern for LDO design, which can be achieved by either using external capacitor or by using some special compensation techniques with improved topologies. There is limit on on-chip capacitor value so for stability off-chip capacitance in combination with effective series resistance is used. But for portable applications there are many LDOs which utilize on-chip capacitor with different specific schemes for compensation. In this paper, LDO design techniques and different topologies to improve its stability and performance have been discussed.