Cost Analysis and Simulation of Decimator for Multirate Applications

Authors

  • Rajesh Mehra NITTTR, Chandigarh
  • Lajwanti Singh AICE, Jaipur

DOI:

https://doi.org/10.24297/ijct.v11i1.1188

Keywords:

ASIC, Decimator, DSP, FIR, FPGA .

Abstract

In this paper, a decimator design has been presented for multirate digital signal processing.  The decimator design has been analysed and simulated for cost comparison in terms of multipliers and MPIS. Two structures  namely Transposed Direct form and Symmetric Direct form have been used performance and  resource consumption analysis. The decimators have been designed  & simulated using MATLAB. It can be observed from the simulated results that symmetric structure comsumes almost 50% less multipliers and MPIS compared to transposed structure. So the symmetric structure based decimator is suitable to provide cost effective solution

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Author Biographies

Rajesh Mehra, NITTTR, Chandigarh

Department Of Electronics & Communication

Lajwanti Singh, AICE, Jaipur

Department Of Electronics & Communication

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Published

2013-10-05

How to Cite

Mehra, R., & Singh, L. (2013). Cost Analysis and Simulation of Decimator for Multirate Applications. INTERNATIONAL JOURNAL OF COMPUTERS &Amp; TECHNOLOGY, 11(1), 2175–2181. https://doi.org/10.24297/ijct.v11i1.1188

Issue

Section

Research Articles